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features description to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pullup SN74ALVCH16240 16-bit buffer/driver with 3-state outputs sces045d ? july 1995 ? revised august 2004 member of the texas instruments widebus? family epic? (enhanced-performance implanted cmos) submicron process esd protection exceeds 2000 v per mil-std-883, method 3015; exceeds 200 v using machine model (c = 200 pf, r = 0) latch-up performance exceeds 250 ma per jesd 17 bus hold on data inputs eliminates the need for external pullup/pulldown resistors package options include plastic 300-mil shrink small-outline (dl) and thin shrink small-outline (dgg) packages this 16-bit buffer/driver is designed for 1.65-v to 3.6-v v cc operation. the SN74ALVCH16240 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. the device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. it provides inverting outputs and symmetrical active-low output-enable (oe) inputs. resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. the SN74ALVCH16240 is characterized for operation from -40c to 85c. function table (each 4-bit buffer) inputs output y oe a l h l l l h h x z please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. widebus, epic are trademarks of texas instruments. production data information is current as of publication date. copyright ? 1995?2004, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. www .ti.com 12 3 4 5 6 7 8 9 10 1 1 1213 14 15 16 17 18 19 20 21 22 23 24 4847 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1oe 1y11y2 gnd 1y31y4 v c c 2y12y2 gnd 2y32y4 3y1 3y2 gnd 3y33y4 v c c 4y14y2 gnd 4y34y4 4oe 2oe 1a11a2 gnd 1a3 1a4 v c c 2a12a2 gnd 2a3 2a4 3a1 3a2 gnd 3a3 3a4 v c c 4a14a2 gnd 4a3 4a4 3oe dgg or dl p ackage (t op view)
logic symbol (1) SN74ALVCH16240 16-bit buffer/driver with 3-state outputs sces045d ? july 1995 ? revised august 2004 2 www .ti.com 47 1a1 46 1a2 44 1a3 43 1a4 1y1 2 1y2 3 1y3 5 1y4 6 41 2a1 40 2a2 38 2a3 37 2a4 2y1 8 2y2 9 2y3 1 1 2y4 12 36 3a1 35 3a2 33 3a3 32 3a4 3y1 13 3y2 14 3y3 16 3y4 17 30 4a1 29 4a2 27 4a3 26 4a4 4y1 19 4y2 20 4y3 22 4y4 23 en1 1 en4 24 1oe 2oe 3oe 4oe en2 48 en3 25 ( 1 ) this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. 1 1 1 2 1 3 1 4
logic diagram (positive logic) absolute maximum ratings (1) SN74ALVCH16240 16-bit buffer/driver with 3-state outputs sces045d ? july 1995 ? revised august 2004 over operating free-air temperature range (unless otherwise noted) min max unit v cc supply voltage range -0.5 4.6 v v i input voltage range (2) -0.5 4.6 v v o output voltage range (2) (3) -0.5 v cc + 0.5 v i ik input clamp current v i < 0 -50 ma i ok output clamp current v o < 0 -50 ma i o continuous output current 50 ma continuous current through each v cc or gnd 100 ma dgg package 89 q ja package thermal impedance (4) c/w dl package 94 t stg storage temperature range -65 150 c (1) stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) this value is limited to 4.6 v maximum. (4) the package thermal impedance is calculated in accordance with jesd 51. 3 www .ti.com 1oe 1a11a2 1a3 1a4 1y11y2 1y3 1y4 147 46 44 43 23 5 6 2oe 2a12a2 2a3 2a4 2y12y2 2y3 2y4 4841 40 38 37 89 1 1 12 3oe 3a13a2 3a3 3a4 3y13y2 3y3 3y4 2536 35 33 32 1314 16 17 4oe 4a14a2 4a3 4a4 4y14y2 4y3 4y4 2430 29 27 26 1920 22 23
recommended operating conditions (1) SN74ALVCH16240 16-bit buffer/driver with 3-state outputs sces045d ? july 1995 ? revised august 2004 min max unit v cc supply voltage 1.65 3.6 v v cc = 1.65 v to 1.95 v 0.65 v cc v ih high-level input voltage v cc = 2.3 v to 2.7 v 1.7 v v cc = 2.7 v to 3.6 v 2 v cc = 1.65 v to 1.95 v 0.35 v cc v il low-level input voltage v cc = 2.3 v to 2.7 v 0.7 v v cc = 2.7 v to 3.6 v 0.8 v i input voltage 0 v cc v v o output voltage 0 v cc v v cc = 1.65 v -4 v cc = 2.3 v -12 i oh high-level output current ma v cc = 2.7 v -12 v cc = 3 v -24 v cc = 1.65 v 4 v cc = 2.3 v 12 i ol low-level output current ma v cc = 2.7 v 12 v cc = 3 v 24 dt/dv input transition rise or fall rate 10 ns/v t a operating free-air temperature -40 85 c (1) all unused control inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs, literature number scba004. 4 www .ti.com
electrical characteristics switching characteristics SN74ALVCH16240 16-bit buffer/driver with 3-state outputs sces045d ? july 1995 ? revised august 2004 over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ (1) max unit i oh = -100 ma 1.65 v to 3.6 v v cc - 0.2 i oh = -4 ma 1.65 v 1.2 i oh = -6 ma 2.3 v 2 v oh 2.3 v 1.7 v i oh = -12 ma 2.7 v 2.2 3 v 2.4 i oh = -24 ma 3 v 2 i ol = 100 ma 1.65 v to 3.6 v 0.2 i ol = 4 ma 1.65 v 0.45 i ol = 6 ma 2.3 v 0.4 v ol v 2.3 v 0.7 i ol = 12 ma 2.7 v 0.4 i ol = 24 ma 3 v 0.55 i i v i = v cc or gnd 3.6 v 5 ma v i = 0.58 v 1.65 v 25 v i = 1.07 v 1.65 v -25 v i = 0.7 v 2.3 v 45 i i(hold) v i = 1.7 v 2.3 v -45 ma v i = 0.8 v 3 v 75 v i = 2 v 3 v -75 v i = 0 to 3.6 v (2) 3.6 v 500 i oz v o = v cc or gnd 3.6 v 10 ma i cc v i = v cc or gnd, i o = 0 3.6 v 40 ma di cc one input at v cc - 0.6 v, other inputs at v cc or gnd 3 v to 3.6 v 750 ma control inputs 3 c i v i = v cc or gnd 3.3 v pf data inputs 6 c o outputs v o = v cc or gnd 3.3 v 7 pf (1) all typical values are at v cc = 3.3 v, t a = 25c. (2) this is the bus-hold maximum dynamic current. it is the minimum overdrive current required to switch the input from one state to another. over recommended operating free-air temperature range (unless otherwise noted) (see figure 1 through figure 3) v cc = 2.5 v v cc = 3.3 v v cc = 1.8 v v cc = 2.7 v from to 0.2 v 0.3 v parameter unit (input) (output) typ min max min max min max t pd a y (1) 1 5.3 5.3 1 3.9 ns t en oe y (1) 1 6.4 6.1 1 5 ns t dis oe y (1) 1 5.4 4.8 1 4.4 ns (1) this information was not available at the time of publication. 5 www .ti.com
operating characteristics parameter measurement information SN74ALVCH16240 16-bit buffer/driver with 3-state outputs sces045d ? july 1995 ? revised august 2004 t a = 25c v cc = 1.8 v v cc = 2.5 v v cc = 3.3 v parameter test conditions unit typ typ typ outputs enabled (1) 16 19 c pd power dissipation capacitance c l = 50 pf, f = 10 mhz pf outputs disabled (1) 4 5 (1) this information was not available at the time of publication. v cc = 1.8 v figure 1. load circuit and voltage waveforms 6 www .ti.com v c c /2 v c c /2 v c c /2 v c c /2 v c c /2 v c c /2 v c c /2 v c c /2 v o h v o l t h t s u from output under t est c l = 30 pf (see note a) load circuit s1 open gnd 1 k w 1 k w output control (low-level enabling) output w aveform 1 s1 at 2 v c c (see note b) output w aveform 2 s1 at gnd (see note b) t p z l t p z h t p l z t p h z 0 v v o l + 0.15 v v o h ? 0.15 v 0 v v c c 0 v0 v t w v c c v c c vol t age w a veforms setup and hold times vol t age w a veforms pulse dura tion vol t age w a veforms enable and disable times t iming input data input input t p d t p l z /t p z l t p h z /t p z h open 2 v c c gnd test s1 notes: a. c l includes probe and jig capacitance. b. w aveform 1 is for an output with internal conditions such that the output is low , except when disabled by the output control. w aveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2 ns, t f 2 ns. d. the outputs are measured one at a time, with one transition per measurement. e. t p l z and t p h z are the same as t d i s . f. t p z l and t p z h are the same as t e n . g. t p l h and t p h l are the same as t p d . 0 v v c c v c c /2 t p h l v c c /2 v c c /2 v c c 0 vv o h v o l input output vol t age w a veforms prop aga tion dela y times v c c /2 v c c /2 t p l h 2 v c c v c c
parameter measurement information SN74ALVCH16240 16-bit buffer/driver with 3-state outputs sces045d ? july 1995 ? revised august 2004 v cc = 2.5 v 0.2 v figure 2. load circuit and voltage waveforms 7 www .ti.com v c c /2 v c c /2 v c c /2 v c c /2 v c c /2 v c c /2 v c c /2 v c c /2 v o h v o l t h t s u from output under t est c l = 30 pf (see note a) load circuit s1 open gnd 500 w 500 w output control (low-level enabling) output w aveform 1 s1 at 2 v c c (see note b) output w aveform 2 s1 at gnd (see note b) t p z l t p z h t p l z t p h z 0 v v o l + 0.15 v v o h ? 0.15 v 0 v v c c 0 v0 v t w v c c v c c vol t age w a veforms setup and hold times vol t age w a veforms pulse dura tion vol t age w a veforms enable and disable times t iming input data input input t p d t p l z /t p z l t p h z /t p z h open 2 v c c gnd test s1 notes: a. c l includes probe and jig capacitance. b. w aveform 1 is for an output with internal conditions such that the output is low , except when disabled by the output control. w aveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2 ns, t f 2 ns. d. the outputs are measured one at a time, with one transition per measurement. e. t p l z and t p h z are the same as t d i s . f. t p z l and t p z h are the same as t e n . g. t p l h and t p h l are the same as t p d . 0 v v c c v c c /2 t p h l v c c /2 v c c /2 v c c 0 vv o h v o l input output vol t age w a veforms prop aga tion dela y times v c c /2 v c c /2 t p l h 2 v c c v c c
parameter measurement information SN74ALVCH16240 16-bit buffer/driver with 3-state outputs sces045d ? july 1995 ? revised august 2004 v cc = 2.7 v and 3.3 v 0.3 v figure 3. load circuit and voltage waveforms 8 www .ti.com v o h v o l from output under t est c l = 50 pf (see note a) load circuit s1 6 v open gnd 500 w 500 w t p l h t p h l output control (low-level enabling) output w aveform 1 s1 at 6 v (see note b) output w aveform 2 s1 at gnd (see note b) t p z l t p z h t p l z t p h z 1.5 v 1.5 v 1.5 v 1.5 v 2.7 v0 v 1.5 v 1.5 v v o h v o l 0 v 1.5 v v o l + 0.3 v 1.5 v v o h ? 0.3 v 0 v 1.5 v 2.7 v 0 v0 v 2.7 v0 v input 2.7 v 2.7 v3 v vol t age w a veforms setup and hold times vol t age w a veforms prop aga tion dela y times vol t age w a veforms pulse dura tion vol t age w a veforms enable and disable times t iming input data input output input t p d t p l z /t p z l t p h z /t p z h open 6 v gnd test s1 1.5 v 1.5 v t w t h t s u 1.5 v 1.5 v notes: a. c l includes probe and jig capacitance. b. w aveform 1 is for an output with internal conditions such that the output is low , except when disabled by the output control. w aveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 2.5 ns, t f 2.5 ns. d. the outputs are measured one at a time, with one transition per measurement. e. t p l z and t p h z are the same as t d i s . f. t p z l and t p z h are the same as t e n . g. t p l h and t p h l are the same as t p d .
package option addendum www.ti.com 10-jun-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples 74alvch16240dggre4 active tssop dgg 48 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 alvch16240 SN74ALVCH16240dggr active tssop dgg 48 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 alvch16240 SN74ALVCH16240dl active ssop dl 48 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 alvch16240 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and
package option addendum www.ti.com 10-jun-2014 addendum-page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant SN74ALVCH16240dggr tssop dgg 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 q1 package materials information www.ti.com 14-jul-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) SN74ALVCH16240dggr tssop dgg 48 2000 367.0 367.0 45.0 package materials information www.ti.com 14-jul-2012 pack materials-page 2

mechanical data mtss003d january 1995 revised january 1998 post office box 655303 ? dallas, texas 75265 dgg (r-pdso-g**) plastic small-outline package 4040078 / f 12/97 48 pins shown 0,25 0,15 nom gage plane 6,00 6,20 8,30 7,90 0,75 0,50 seating plane 25 0,27 0,17 24 a 48 1 1,20 max m 0,08 0,10 0,50 0 8 56 14,10 13,90 48 dim a max a min pins ** 12,40 12,60 64 17,10 16,90 0,15 0,05 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold protrusion not to exceed 0,15. d. falls within jedec mo-153
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